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Samsung Electronics Revises Roadmap for Next Generation DRAM "D0a," Pulls Hybrid Bonding Forward Samsung Electronics has revised its next generation DRAM development strategy. The company recently moved "B1b," a technology that had been under development as a standalone project, onto its official roadmap and designated it "D0a," its first DRAM below 10 nanometers (nm). D0a originally referred to Samsung's vertical channel transistor (VCT) DRAM process. VCT DRAM has now been reclassified under a separate name, "D0a-V." Samsung changed the D0a designation to accelerate the adoption of advanced packaging in commodity DRAM. B1b refers to a technology that uses wafer to wafer (W2W) hybrid bonding to increase internal integration density. "B1b was in R&D, but it was not on Samsung's official roadmap," said a source familiar with the matter. "With this strategy revision, it has been folded into D0a. It means Samsung is actively pushing for fast commercialization of B1b DRAM." Samsung Shifts D0a Designation from VCT DRAM to B1b According to ZDNet Korea's reporting on the 23rd, Samsung has changed the definition of its next generation D0a DRAM from VCT DRAM to B1b. DRAM has advanced by shrinking internal circuit linewidths. The most recently commercialized DRAM is 1c (sixth generation 10nm class), with linewidths of around 11 to 12nm. The next product, 1d (seventh generation 10nm class), comes in at 10 to 11nm and is effectively the last 10nm class DRAM. These linewidth figures are marketing terms used to indicate performance, not actual physical dimensions. Samsung has pursued several technological shifts to realize D0a, the first sub 10nm DRAM. B1b is the most prominent of these. B1b fabricates the memory cells and the surrounding driver circuitry, known as the peri, on separate wafers and then bonds them together, stacking the cell on top of the peri. Compared with the conventional approach of integrating both cell and peri on a single wafer, this allows the cells to be packed more densely. It also lets each of the cell and the peri use a process optimized for it. B1b uses W2W hybrid bonding. Hybrid bonding joins chips by directly connecting their copper interconnects. Compared with conventional packaging that connects chips through small bumps, it improves integration density and performance. W2W hybrid bonding is also entering full scale adoption in high layer count NAND of 400 layers or more. W2W means bonding one wafer to another. Why Samsung Is Prioritizing B1b: "VCT DRAM Needs More Time" VCT DRAM, previously called the D0a process, has been renamed D0a-V as a derivative. VCT stands up the transistor inside the DRAM cell, the smallest unit that stores data, vertically instead of laying it horizontally. Making the transistor vertical reduces cell area. The conventional cell area, calculated by multiplying the feature size (F) in each direction, is 6F². VCT can bring this down to 4F². A smaller cell means more cells can be integrated in the same area. VCT DRAM, however, is considered extremely difficult technically. It requires high aspect ratio etching to form vertical transistors and new materials to address the rise in leakage current that comes with smaller cell area. W2W hybrid bonding, as used in B1b, is already in volume production in existing semiconductor processes such as CMOS image sensors and high layer count NAND. This appears to be why Samsung moved B1b ahead of VCT DRAM in priority for implementing the D0a process. "From a design standpoint, B1b has a lower barrier to commercialization than VCT, so the industry sees early adoption of B1b as likely," another source said. "Inside Samsung, too, the mood is to move faster on B1b than on VCT." **B1b to Play a Major Role in Next Generation AI Memory "HBM5"** B1b could also play a significant role in Samsung's next generation high bandwidth memory (HBM) business. Samsung is currently reviewing applying B1b to HBM5 (eighth generation). HBM5 is expected to enter mass production around 2029. Samsung is developing the product with a target of raising operating speed by roughly 50% or more over its predecessor, HBM4E. Commercialization of B1b based D0a DRAM is estimated to be at least two years away. The industry expects the specific mass production investment schedule to be finalized around the middle of next year. VCT DRAM development is continuing in parallel. The industry view is that VCT DRAM and 3D DRAM could eventually be developed on top of B1b. 3D DRAM stacks the cells themselves vertically and is expected to follow VCT DRAM. "B1b will ultimately be applied alongside VCT DRAM or 3D DRAM," said Choi Jeongdong, Senior Vice President at TechInsights. "Manufacturing the cell and peri separately brings many advantages, so hybrid bonding will serve as a platform applied together with future DRAM cell architectures."

JPM has updated its HBM model and now expects 16Hi HBM adoption in 2029 at the earliest. Good morning.

According to a report from Taiwan's DigiTimes, the arrangement in which CXMT and YMTC each handled DRAM and NAND respectively is changing, and the relationship between the two companies is turning hostile. YMTC is moving into LPDDR5 DRAM and aims to begin trial production by the end of 2026, while CXMT is also looking to expand beyond DRAM into NAND flash. The industry expects the two Chinese memory makers to clash head to head as early as 2028. With YMTC having already advanced to 270 layers through its Xtacking technology, patent disputes are expected to become the key battleground in this contest for the top position in Chinese memory. As the memory industry enters a supercycle, YMTC plans to start production at its Phase 3 project by the end of 2026. Initially it is planning DRAM capacity of roughly 25,000 wafers, and it is expected to complete capacity expansion and stabilization in 2027. It is pursuing LPDDR5 as its first mass production target, while also securing space for further expansion. CXMT does not appear willing to fall behind. Recent reports indicate it will build a NAND research and development and production line in Beijing. There is also talk in the market that CXMT has been recruiting personnel from inside YMTC. lol Originally, under the Chinese government's supply chain localization policy, the two companies developed technology and capacity in their own respective domains, in the spirit of "even brothers climb the mountain on their own." But as Chinese memory makers have grown rapidly, the competitive dynamic has become increasingly clear, and both are now shifting toward building their own cooperative ecosystems. DigiTimes points out that supply chain vendors may in turn find themselves having to pick a side. According to industry sources, it remains unclear when CXMT's production line will come online, with mass production expected in 2028 to 2029 at the earliest. The key question, however, is how CXMT will work around YMTC's technology and patents.

Congrats to AMD holders. Intel’s next, right? https://t.co/ix8RbOe3zw

I’m not sure Intel has secured enough substrate capacity to support all these customers. And… Qualcomm’s CPU is codenamed Rolex? That’s pretty cool. $INTC https://t.co/jV5uCLZb4N

@Alex_Intel_ Even if you built a CPU neocloud, Intel and AMD would probably push back.

BofA's Simon Woo has put out a report, and there's some interesting content in it. To quote a portion: - Recent checks with memory makers, spot market distributors, and OEMs point to firm 3Q ASPs: despite a rising LTA mix, 3Q ASPs for most DRAM products rose 20 to 30% quarter on quarter, and NAND rose more than 15% - High single digit ASP increases expected in 4Q as well. Also a notable change: hyperscalers have signed new contracts agreeing to pay higher DRAM ASPs in 1Q27 than in 4Q26 - On 2H ASPs, the existing optimistic view is maintained, with no change to estimates. However, the stance on 1H27 has turned more positive given the persistent memory supply shortage and the aggressive race among OEMs and big tech to secure chips - Accordingly, 2027 to 2028 DRAM/NAND ASP assumptions are raised by 8 to 12% and 2 to 3%, respectively. That said, ASPs are expected to decline around 10% in 2028 (DRAM down 5%, NAND down 13%), which is interpreted as a soft landing phase ahead of renewed growth in 2029 to 2030

SK hynix Subsidiary Solidigm Pursues Its First U.S. NAND Fab Solidigm, the NAND subsidiary of SK hynix, is reviewing the construction of its first NAND mass production line in the United States, it was learned on the 19th. The company is currently working through details such as the fab site and the timing of the investment. With NAND demand surging on the expansion of AI infrastructure buildouts, the move is being read as a strategy to strengthen cooperation with customers in the U.S. It also lines up with the push to expand U.S. AI investment that SK Chairman Chey Tae won has been leading at the group level. Solidigm is the U.S. entity SK hynix established when it acquired Intel's NAND flash business at the end of 2021. The total deal size was $9 billion (about 10 trillion won at the exchange rate of the time). Solidigm operates Fab 1 in Dalian, China, and began capital spending on Dalian Fab 2 in the third quarter of this year. In the U.S. it has only its headquarters and an R&D center, with no production base. The region Solidigm is considering for its first U.S. production base is the East Coast. The company is understood to be discussing the details, including site selection, product mix and the timing of mass production. A person familiar with the matter said, "Solidigm is pursuing a local mass production line to respond to NAND demand for AI servers from U.S. big tech companies," adding that "it will firm up its investment plan based on long term agreement (LTA) negotiations with customers." Solidigm has so far focused on developing quad level cell (QLC) NAND for AI data centers. QLC stores four bits in a single cell, the smallest unit of data storage. Compared with other approaches such as triple level cell (TLC), which stores three bits, it is better suited to building high capacity SSDs. Orders for high capacity NAND have been piling up in particular as the NAND capacity required by next generation AI platforms such as Nvidia's Blackwell and Vera Rubin climbs sharply. According to market research firm TrendForce, NAND revenue at SK hynix (including Solidigm) reached $14.2729 billion (about 19.8 trillion won) in the second quarter of this year, up 89.5% from the previous quarter. Solidigm's U.S. investment fits with the broader expansion of U.S. investment that SK Group is pursuing. Following the listing of SK hynix American depositary receipts (ADR) and the construction of an advanced packaging fab in the U.S., SK Group is also leaving the door open to building an additional memory production plant. Solidigm itself is preparing an initial public offering (IPO) on the Nasdaq. At an event in New York in July marking the SK hynix ADR listing, Chairman Chey said, "In addition to the advanced packaging facility in Indiana, we are reviewing further investments," and "if conditions such as power, water, workforce and supply chain are in place, building a memory production plant is also possible." More recently, talk of SK hynix and Intel cooperating on memory production in the U.S. has also surfaced through foreign media and industry sources. It will take time before anything is finalized, but the industry view is that it is feasible, given that U.S. demand for AI memory such as high bandwidth memory (HBM) is expected to keep growing over the medium to long term. Regarding its U.S. capital investment plans, a Solidigm official said, "We are reviewing various options to strengthen our business competitiveness, but nothing has been decided." $SKHY

Remember that SK hynix said “We have no plans for an ADR listing” even before it listed its ADRs. https://t.co/zuHhJcykCy

Not many people are paying attention, but what matters in the Hynix and Intel news is that Hynix and Intel could form a JV with hyperscalers hungry for memory supply. That's more important than the Hynix and Intel news itself.