郭明錤｜Ming-Chi Kuo

MediaTek’s latest announcement on the deepening of its long-term partnership with Nvidia repeatedly uses the term “rack-scale.” This is the key to understanding the announcement, and it directly validates the central conclusion of my research from more than two months ago: MediaTek has upgraded the strategic positioning of its AI business from "IC / ASIC design" to "system-level design." The announcement link: https://t.co/Yf4XOFVvSH The announcement also explains how MediaTek plans to put this new positioning into practice. By working with Nvidia, MediaTek can bring custom chips and XPUs into Nvidia’s mature rack-scale ecosystem, so that once chip development is complete, they can be integrated more quickly into rack-scale systems for deployment in data centers and AI factories. For MediaTek, Nvidia’s mature rack-scale systems ecosystem means it does not need to start from scratch, giving this new strategy a much clearer path to execution. For Nvidia, MediaTek’s custom silicon design capabilities and customer base can help extend Nvidia’s rack-scale ecosystem further into the custom silicon market. This also explains why “rack-scale” is the key term in the announcement: it is where the two companies need each other most. MediaTek can move from chips to systems, while Nvidia can extend its rack-scale ecosystem into the custom silicon market, creating a win-win that opens up new growth opportunities for both.

聯發科最新公告宣布深化與 Nvidia 的長期合作，其中反覆出現的「rack-scale」，正是理解這份公告的關鍵，也直接驗證了我兩個多月前研究的核心判斷： 聯發科內部已將 AI 事業的策略定位，從「IC / ASIC 設計」提升至「系統級別設計」。 公告網址： https://t.co/Yf4XOFVvSH 這份公告也進一步說明，聯發科將如何執行這項新定位：透過與 Nvidia 合作，把客製化晶片 / XPU 導入 Nvidia 已成熟的機櫃級生態，讓客製化晶片在完成開發後，能更快整合成可部署於資料中心與 AI 工廠的機櫃級系統。 對聯發科而言，Nvidia 已成熟的機櫃級系統生態，使其不必從零開始，也讓新策略更具可執行性。 對 Nvidia 而言，聯發科的客製化晶片設計能力與客戶基礎，可協助其機櫃級生態進一步延伸至自研晶片市場。 這也說明了為何 rack-scale 是這份公告的關鍵字：這正是雙方最需要彼此的地方。聯發科藉此從晶片走向系統，Nvidia 則將機櫃級生態延伸至客製化晶片市場，形成雙方都能開拓新成長空間的雙贏局面。

Just as the market had come to believe that Rubin CPX had been dropped from Nvidia’s product roadmap, my latest industry checks indicate that Nvidia has revived the program, with production expected to begin in 1Q27. Compared with the previous design, the revived Rubin CPX delivers stronger prefill performance and features major changes to both its GPU specifications and rack architecture, underscoring the high priority Nvidia places on prefill solutions. Key changes: 1. Rubin CPX GPU specs CPX delivers near-Rubin compute performance and matches Rubin’s maximum power rating of 2,300 W per GPU. CPX moves to 168 GB of HBM4, vs. 288 GB on Rubin and 128 GB of GDDR7 on the previous CPX design. 2. Rack design The new CPX uses a standalone MGX ETL rack rather than sharing a rack with Rubin, as in the previous design. Customers can opt for 64, 128, 192, or 256 CPX GPUs depending on their needs. Within a CPX rack, each group of 64 CPX GPUs forms a rack module comprising eight compute trays (eight CPX GPUs per tray) and one switch tray. 3. Scale-up and scale-out NVLink is used only for scale-up among the eight CPX GPUs within each tray, with 1–1.5 TB/s of NVLink bandwidth per CPX (vs. 3.6 TB/s per Rubin). Inter-tray scale-out within each rack module runs over Spectrum-6 Ethernet using all-copper L1 links. Across rack modules, scale-out is handled by each module’s Spectrum-6 switch over OSFP optical links. 4. How it works CPX must be paired with Vera Rubin NVL72, and Nvidia recommends a 1:1 ratio of CPX to Rubin GPUs. CPX handles prefill and builds the KV cache, which is then transferred to Rubin over Ethernet RDMA for decode. 5. Product positioning: Best performance per dollar for long-context prefill Over 50% of today’s AI inference workload comes from processing input context and building the corresponding KV cache. CPX therefore offers a more flexible, lower-cost way to handle prefill. Each eight-CPX tray has approximately 1.34 TB of HBM4, sufficient for most long-context prefill workloads and associated KV cache requirements.

正當市場認為 Rubin CPX 已被 Nvidia 從產品藍圖中移除之際，我最新的產業調查顯示，Nvidia 已重啟 Rubin CPX，預計於 1Q27 開始生產。相較舊版，重啟後的 Rubin CPX 擁有更強的預填充（prefill）效能，GPU 規格與機櫃架構也都有明顯改變，足以證明 Nvidia 對 prefill 方案的高度重視。 關鍵改變如下： 1. Rubin CPX GPU 規格 CPX 算力接近 Rubin，單顆 GPU 最高功耗也同為 2,300 W。CPX 記憶體改為 168 GB HBM4，低於 Rubin 的 288 GB HBM4，但高於舊版 CPX 的 128 GB GDDR7。 2. 機櫃設計 新版 CPX 採用獨立的 MGX ETL 機櫃，不再像舊版與 Rubin 共櫃。客戶可依需求配置 64、128、192 或 256 顆 CPX。在 CPX 機櫃中，每 64 顆 CPX 組成一個機櫃模組，每個機櫃模組配置 8 個運算托盤（每個托盤有 8 顆 CPX）與 1 個交換機托盤。 3. Scale-up 與 scale-out NVLink 僅用於同一托盤內 8 顆 CPX GPU 的 scale-up，每顆 CPX 的 NVLink 頻寬為 1–1.5 TB/s（vs. 每顆 Rubin 的 3.6 TB/s）。同一機櫃模組內的托盤間，透過 Spectrum-6 Ethernet（全銅 L1）進行 scale-out；跨機櫃模組時，則由各模組的 Spectrum-6 透過 OSFP 光纖進行 scale-out。 4. 運作方式 CPX 需與 Vera Rubin NVL72 搭配，Nvidia 建議 CPX 與 Rubin 的比例為 1:1。CPX 負責預填充（prefill）並建立 KV cache，再透過 Ethernet RDMA 傳給 Rubin 執行解碼生成（decode）。 5. 產品定位：長上下文 prefill 的最高性價比方案 目前 AI 推論工作量中，超過一半來自處理輸入內容（context）並建立相對應的 KV cache，因此，CPX 以更彈性的部署方式與更低成本承接 prefill。每個運算托盤（有 8 個 CPX）約有 1.34 TB HBM4，足以支援大多數長上下文 prefill 與 KV cache 建立需求。

A recent media report claims that tight DRAM supply has left TSMC holding around US$1 billion worth of Apple 2nm processor work-in-process (WIP), described in the report as “processor wafers,” that cannot yet be packaged. As supporting evidence, it points to TSMC’s 2Q26 earnings call, where the company said the increase in inventory days was mainly due to the 2nm production ramp. My industry checks suggest that Apple has indeed scaled back its hardware shipment plans this year due to memory shortages. However, Apple plans its processor production at TSMC at least three months in advance, based on the amount of memory expected to be available, rather than having TSMC build large amounts of WIP ahead of time. This does not mean TSMC never builds WIP in advance and holds it in inventory. But if the bottleneck is not at TSMC, building ahead provides little benefit, so Apple would have little reason to pay TSMC extra for it. In other words, tight memory supply is real. But my understanding is that there has been no dramatic scenario in which TSMC first built up US$1 billion of WIP and then had to wait for memory to arrive before packaging could proceed. TSMC and Apple are both known for world-class execution, and such a dramatic development would be unusual given how closely the two companies coordinate their supply chains. Finally, public information alone offers a useful way to assess this claim. TSMC said on its 2Q26 earnings call that the increase in inventory days was mainly due to the 2nm production ramp. However, that inventory cannot be directly attributed to Apple processor WIP for three reasons: 1. TSMC's inventory days typically increase when a new advanced node enters its initial production ramp, so this is not unique to this year. 2. TSMC’s definition of inventory includes not only work-in-process, but also finished goods, raw materials, supplies, and spare parts. 3. Apple is not TSMC’s only 2nm customer this year. Other chip designers, including AMD and MediaTek, are also using 2nm.

A recent media report claims that tight DRAM supply has left TSMC holding around US$1 billion worth of Apple 2nm processor work-in-process (WIP), described in the report as “processor wafers,” that cannot yet be packaged. As supporting evidence, it points to TSMC’s 2Q26 earnings call, where the company said the increase in inventory days was mainly due to the 2nm production ramp. My industry checks suggest that Apple has indeed scaled back its hardware shipment plans this year due to memory shortages. However, Apple plans its processor production at TSMC at least three months in advance, based on the amount of memory expected to be available, rather than having TSMC build large amounts of WIP ahead of time. This does not mean TSMC never builds WIP in advance and holds it in inventory. But if the bottleneck is not at TSMC, building ahead provides little benefit, so Apple would have little reason to pay TSMC extra for it. In other words, tight memory supply is real. But my understanding is that there has been no dramatic scenario in which TSMC first built up US$1 billion of WIP and then had to wait for memory to arrive before packaging could proceed. TSMC and Apple are both known for world-class execution, and such a dramatic development would be unusual given how closely the two companies coordinate their supply chains. Finally, public information alone offers a useful way to assess this claim. TSMC said on its 2Q26 earnings call that the increase in inventory days was mainly due to the 2nm production ramp. However, that inventory cannot be directly attributed to Apple processor WIP for three reasons: 1. TSMC's inventory days typically increase when a new advanced node enters its initial production ramp, so this is not unique to this year. 2. TSMC’s definition of inventory includes not only work-in-process, but also finished goods, raw materials, supplies, and spare parts. 3. Apple is not TSMC’s only 2nm customer this year. Other chip designers, including AMD and MediaTek, are also using 2nm.

市場近期傳聞，台積電因 DRAM 供應緊張，囤積約 10 億美元的 Apple 2nm 處理器半成品（傳聞稱為處理器晶圓）無法封裝，並以台積電 2Q26 法說提到「庫存天數增加主因是 2nm 量產爬坡」作為佐證。 我的產業調查顯示，Apple 今年的硬體出貨量確實因記憶體短缺而下調，但 Apple 在台積電的處理器訂單，會在至少約 3 個月前依可取得的記憶體數量規劃生產，而不是讓台積電提前大量生產半成品。 這不代表台積電不會提前生產並囤積半成品；但若瓶頸不在台積電，這麼做並無實益，因此，Apple 也沒有太大理由額外付錢要求台積電這樣做。 換言之，記憶體供應緊張是真，但我的理解是，並沒有出現「台積電先囤積 10 億美元半成品，再苦等記憶體到貨封裝」這種戲劇性變化。台積電與 Apple 都是全球執行力頂尖的企業，在供應鏈管理上，雙方緊密合作下也很難出現這種戲劇性的發展。 最後，憑公開資訊也能反思市場傳聞可能性。台積電在 2Q26 法說表示，庫存天數增加主要因 2nm 量產爬坡，但這裡的庫存不能直接視為由 Apple 處理器半成品造成，原因有三： 1. 台積電過往全新先進製程量產爬坡時，庫存天數通常也會增加，並非今年特有現象。 2. 台積電的庫存除半成品外，也包括製成品、原材料、物料與備品。 3. 今年 2nm 客戶不只有 Apple，還包括其他 IC 設計客戶（如 AMD 與聯發科）。

A few quick thoughts on what TSMC said about CoPoS during its Q2 2026 earnings call (screenshot from the transcript). The devil is in the details: 1. The phrase "alternative to try to lower down the cost" refers to the glass carrier. That's the CoP part. 2. "Work with substrate vendor" refers to the glass core substrate (GCS). That's the oS part. 3. Pay close attention to this phrase: "takes about another 1 year to be mature." It refers to the pilot line mentioned earlier. For a new technology, a mature pilot line and a mature mass-production line are two completely different things. 4. When TSMC says the pilot line will mature in about a year, this fully validates my earlier prediction that "the 510x515mm format will be used for pre-mass-production simulation in 2H27." For oS/GCS, "mature" means being able to start simulating with the final 510x515mm glass format on the pilot line, instead of the current 250x250mm. 5. Following from point 4, most companies currently involved in the oS/GCS supply chain may not be among the suppliers ultimately selected for mass production (not to mention companies that are only part of the market narrative and have no actual involvement). This is important to keep in mind when looking for investment opportunities at this stage, especially among equipment and materials suppliers. 6. TSMC's answer was brief, but it covered both CoP and oS. It did not mention a glass interposer at all, consistent with my earlier point that CoPoS does not use one. 7. Compared with what TSMC shared at its Japan symposium in June, the only new information in the Q2 2026 earnings call was that the pilot line is expected to reach maturity in 2H27. That said, I think the market was probably already expecting something close to this timeline. Now that TSMC has mentioned it, Ibiden and Innolux may also discuss the same timeline in their upcoming earnings calls.

A few quick thoughts on what TSMC said about CoPoS during its Q2 2026 earnings call (screenshot from the transcript). The devil is in the details: 1. The phrase "alternative to try to lower down the cost" refers to the glass carrier. That's the CoP part. 2. "Work with substrate vendor" refers to the glass core substrate (GCS). That's the oS part. 3. Pay close attention to this phrase: "takes about another 1 year to be mature." It refers to the pilot line mentioned earlier. For a new technology, a mature pilot line and a mature mass-production line are two completely different things. 4. When TSMC says the pilot line will mature in about a year, this fully validates my earlier prediction that "the 510x515mm format will be used for pre-mass-production simulation in 2H27." For oS/GCS, "mature" means being able to start simulating with the final 510x515mm glass format on the pilot line, instead of the current 250x250mm. 5. Following from point 4, most companies currently involved in the oS/GCS supply chain may not be among the suppliers ultimately selected for mass production (not to mention companies that are only part of the market narrative and have no actual involvement). This is important to keep in mind when looking for investment opportunities at this stage, especially among equipment and materials suppliers. 6. TSMC's answer was brief, but it covered both CoP and oS. It did not mention a glass interposer at all, consistent with my earlier point that CoPoS does not use one. 7. Compared with what TSMC shared at its Japan symposium in June, the only new information in the Q2 2026 earnings call was that the pilot line is expected to reach maturity in 2H27. That said, I think the market was probably already expecting something close to this timeline. Now that TSMC has mentioned it, Ibiden and Innolux may also discuss the same timeline in their upcoming earnings calls.

In the fast-moving tech industry, can data from industry checks go six months without an update and still track a company’s guidance more closely than market consensus? That’s rare, but here’s one example where the research held up, with a little luck on my side. ASML's latest Q2 2026 results further validate several predictions I made six months ago (in January). The most important of them, and the easiest to verify with hard numbers, is the EUV shipment outlook. EUV is different from consumer electronics, where forecasts shift constantly. Strong AI demand and the difficulty of expanding upstream capacity mean that my EUV shipment estimates, based on capacity changes at the key supplier Carl Zeiss SMT, have stayed closer to the company's guidance than the market consensus over the past six months, even without any updates. ASML's 2026 / 2027 EUV shipments: 1. In January, I forecast 2026 / 2027 shipments of 67 / 80-85 units, and noted that 2027 EUV was already sold out. At the time, the market consensus for 2026 shipments was just 53-55 units. 2. In its Q1 2026 results in April, ASML gave shipment guidance of at least 60 / 80 units for 2026 / 2027. Notably, the first time the company offered guidance as far out as 2027, the number already fell within my January forecast range. 3. In its latest Q2 2026 results in July, ASML raised the 2026 / 2027 numbers to about 65 units (excluding High-NA) / about 85 units (implied by the company's guidance), and noted that nearly all the EUV orders it needs for 2027 are already in, bringing the outlook even closer to my January forecast of 67 units for 2026 and "sold out" for 2027. Worth noting: even though more bullish expectations of around 90 units or more for 2027 had surfaced ahead of the Q2 2026 results, the outlook the company ultimately provided (about 85 units) still landed at the upper end of my January forecast range.